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Nagarajan Ranganathan Nagarajan "Ranga" Ranganathan, Ph.D.

Distinguished University Professor

Department of Computer Science and Engineering

University of South Florida

4202 E. Fowler Ave

Tampa, FL-33620

Phone: (813) 974 - 4760

Fax: (813) 974 - 5456

Email: ranganat@cse.usf.edu

Office : ENB 2581

Office Hours:

For Curriculum Vitae CLICK HERE

Research Interests

 VLSI System Design, Design Automation, Energy and Power Optimization, Biomedical Information Processing, Crisis Management and Homeland Security Applications, Computer Architecture and Parallel Computing.

Highlights
  • Associate Editor, ACM Transactions on Design Automation of Electronic Systems, 2007-2010.
  • IEEE Circuits and Systems Society VLSI Transactions Best Pape Award, 2009 for the paper: V. Mahalingam, N. Ranganathan and J. E. Harlow, Fuzzy Optimization Approach for Gate Sizing in the presence of Process Variations, IEEE Transactions on VLSI Systems, 16(8), Pp. 975-984, Aug. 2008.
  • Best Paper Award, ranked 1 out of 360 submissions: N. Hanchate and N. Ranganathan, ”A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise”, Proc. Intl. Conf. on VLSI Design, Jan 2006.
  • IEEE Liaison and Publications Chair, Intl. Conference on VLSI Design 2006
  • Best Paper Award, Intl. Conf. on VLSI Design, Jan 2004, ”Gate Sizing and Buffer Insertion Using Economic Models for Power Optimization,” co-authored with A.Murugavel.
  • Sigma Xi Tampa Bay Chapter, Outstanding Faculty Researcher Award (2004)
  • USF Theodore and Venette Askounes-Ashford Distinguished Scholar Award (2003)
  • USF President’s Award for Faculty Excellence (2002-03)
  • USF Division of Sponsored Research Outstanding Research Achievement Award (2002)
  • Editor-in-Chief, IEEE Transactions on VLSI Systems
  • Co-PI, The IGERT SKINS Project
  • Fellow of IEEE, for contributions to algorithms and architectures for VLSI systems design, Jan 2002.
  • Editor-In-Chief, IEEE Transactions on VLSI Systems, two terms, Jan 2003 to Jan 2007.
  • Best Paper Award, , Intl. Conf. on VLSI Design, 1995, ”JAGUAR: A VLSI Chip for JPEG Image Compression Standard,” co-authored with M. Kovac.
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